FIG. 1 illustrates a logic circuit CL of inverter type coupled between a first terminal B1, which is intended to receive a supply voltage Vdd, and a second terminal B2, which is intended to receive a reference voltage, ground GND for example here. The logic circuit conventionally comprises an input terminal E and an output terminal S.
The output terminal S may here be coupled to the input of another component of the integrated circuit CI (not shown), for example to another inverter. This coupling may generate parasitic capacitances, due for example to the gate capacitances of the transistors of the other inverter.
In FIG. 1, this parasitic capacitance has been represented by a first capacitor C1.
The logic circuit CL conventionally includes an NMOS transistor TN1 coupled in series with a PMOS transistor TP1 between the first terminal B1 and the second terminal B2. The input terminal E of the logic circuit is coupled to the gates of the two transistors, and the output terminal S is coupled to the node common to the two transistors, here the node common to the drain of the PMOS transistor TP1 and to the drain of the NMOS transistor TN1.
Thus, when the signal present on the input terminal E transitions from a high state to a low state, the PMOS transistor TP1 turns on and the NMOS transistor TN1 turns off. The capacitor C1 then charges by virtue of the current IC1 flowing through the PMOS transistor TP1. Since the charging time of the capacitor is very short, this current may be likened to a charging current peak Ic1.
In addition, the simultaneous switching of the two transistors creates, during a short time interval, a short-circuit between the terminals B1 and B2. The length of this time interval increases as the switching speed decreases. Thus, each time the transistors are switched, a short-circuit current peak Ic2 flows between the first terminal B1 and the second terminal B2 through the two transistors TP1 and TN1.
The current peak generated during a transition of the signal delivered by the output terminal S from a low state to a high state may have a different value to that of the current peak generated during a transition from a high state to a low state.
During a transition of the signal present on the input terminal E from a high state to a low state, the logic circuit CL consumes a current higher than the current that it consumes during a transition from a low state to a high state, since in the first case the current consumed is the sum of the current Ic1 charging the capacitor C1 and the short-circuit current and in the second case the current consumed corresponds only to the short-circuit current Ic2.
Thus, by analyzing the current consumption of an integrated circuit including one or more logic gates, for example, using an electromagnetic probe and dedicated algorithms, it is possible to obtain information on the operations performed and on the data manipulated and/or on their occurrences.
It is therefore recommended to mask as much as possible the current consumption of the integrated circuit.
Solutions for masking the current consumption of an integrated circuit, such as for example the dual rail technique, which smooths the current consumption of an integrated circuit by generating a current that is complementary to the current actually consumed by the logic circuits of the circuit, already exist.
This being so, this solution is constraining since it also implies masking the current consumption of logic gates the consumption of which does not need to be masked. Moreover, this technique is costly in real estate, since it requires the number of logic gates in the integrated circuit to be doubled.